Integrated circuits are typically fabricated with multiple levels of patterned metallization electrically separated by interlayer dielectrics which contain vias at selected locations to provide electrical connections between the patterned metallization layers. As integrated circuits are scaled to smaller dimensions in a continual effort to provide increased performance (e.g., by increasing device speed and providing greater circuit functionality within a given area chip), the interconnect linewidth dimension becomes increasingly narrow which renders them more susceptible to deleterious effects such as electromigration and stress migration.
While electromigration refers to mass transport of the materials which comprise the interconnects in response to electrical current conduction, stress migration refers to mass transport of the interconnect material in response to mechanical stress gradients present in the interconnects which result from thermal expansion coefficient mismatches and compliance mismatches between the conductive runners and surrounding (e.g., overlying and/or underlying) dielectric materials. Depending on the thermal history, the stress may be either compressive or tensile. Tensile stress can cause void formation, whereas compressive stress can cause hillock formation. Voids continue to grow to reduce the stress until it is energetically unfavorable for them to continue to grow, and migrating voids may also coalesce with other voids thus providing an effective void growth mechanism.
For instance, consider the process of depositing an interlayer dielectric over an aluminum (Al) line (often termed "runner") which rests on a substrate or other dielectric material overlying a semiconductor substrate. Typically, such deposition is performed by chemical vapor deposition (CVD) at a temperature of at least 350.degree. C. After deposition, as the structure cools toward room temperature, the Al line, having a thermal expansion coefficient much greater than the interlayer dielectric, wishes to contract more than the overlying interlayer dielectric. The interlayer dielectric, which has very good adhesion to the Al layer, prevents the Al line from contracting to its desired equilibrium length, thus resulting in a tensile stress in the Al line. The tensile stress is greatest at the edges of the line and decreases toward the center; hence there is a non-zero tensile stress gradient across the width of the line. This stress gradient corresponds to a chemical potential gradient which represents a thermodynamic driving force for mass transport. Accordingly, Al atoms diffuse to reduce the overall strain energy in the Al line. Over time, typically many months or several years, this mass transport of the conductive layer generates voids in the conductive runners which can lead to failure: the voids may entirely traverse the line (i.e., open circuit), or may reduce the cross-sectional area through which current may be conducted such that electromigration effects are exacerbated and/or current conduction causes a catastrophic thermal failure event.
Essential to improving the electromigration and stress migration properties of conductive runners, is a method for evaluating these effects. Particularly, such methods should accelerate the deterioration mechanisms which may take several years when the devices are subject to storage and/or to normal operating conditions, but must not introduce additional factors which would affect void formation and growth in a manner that would not occur under normal conditions and which would thus result in either false positives or false negatives with respect to interconnect reliability. That is, the evaluation method should mimic the deterioration mechanisms and processes present in the field, only at an accelerated rate such that evaluation is practicable and processing techniques for improving stress migration characteristics may be accurately and objectively characterized within a time frame suitable for developing current devices, and reliability of these devices may be accurately characterized.
Despite continuous efforts to evaluate interconnect reliability, failure of sub-micron width conductive runners due to voiding caused by stress migration has been observed by the present inventors, and by others, in devices fabricated according to processes which satisfied various known interconnect reliability tests, after being stored under normal storage conditions for many months to several years.
There remains a need, therefore, for further improvements in assessing stress migration, and particularly, a need for a stress migration evaluation method which accurately characterizes the deterioration mechanisms in, and long term reliability of, conductive runners fabricated according to various fabrication processes.